Synopsys CoreTools vW-2024.09-SP2
Synopsys Inc., a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs, has released coreTools vW-2024.09-SP2 is a set of intellectual property (IP) packaging and integration tools for use in a knowledge-based design and verification flow.
The coreTool family includes:
coreBuilder – a robust packaging tool that allows designers to capture the knowledge and design intent of the IP and provide graphical or command based configuration menus for the IP. It supports the packaging of all the different model views of the IP needed engineering teams. This reduces IP support costs, improves quality and IP packaged with coreBuilder is fully compliant with the IP-XACT specification.
coreAssembler – an open IP assembly tool that automatically generates the interconnect and configured RTL, as well as documenting the block and system configuration details and design testbench. When combined with coreBuilder, entire subsystems can be packaged as coreKits enabling the easy creation configurable market targeted platforms. In addition to assembly and configuration designers are able to generate a starting testbench configured for the design so they can begin to validate there design. coreAssembler also will generate the IP-XACT XML for the design.
coreConsultant – the utility package for configuring, implementing and validating individual IP blocks packaged with coreBuilder. coreConsultant will also generate the IP-XACT XML for the IP block.
The Synopsys family of coreTools is a comprehensive set of intellectual property (IP) packaging and integration tools for
use in a knowledge-based design and verification flow. The tools enable designers to realize maximum productivity gains
when using IP in their desing. By using an IP-based design and verification flow with IP packaged for assembly, the risk
configuration, and subsystem integration errors is virtually eliminated, and designers have seen over a 60% reduction in
SoC or platform design time and achieve the highest QoR in the implementation of the design
Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia.
Owner: Synopsys Inc.
Product Name: coreTools
Version: vW-2024.09-SP2
Supported Architectures: x86_64
Languages Supported: english
System Requirements: Linux *
Synopsys CoreTools vW-2024.09-SP2 | 644 mb
Download
*
Synopsys Inc., a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs, has released coreTools vW-2024.09-SP2 is a set of intellectual property (IP) packaging and integration tools for use in a knowledge-based design and verification flow.
The coreTool family includes:
coreBuilder – a robust packaging tool that allows designers to capture the knowledge and design intent of the IP and provide graphical or command based configuration menus for the IP. It supports the packaging of all the different model views of the IP needed engineering teams. This reduces IP support costs, improves quality and IP packaged with coreBuilder is fully compliant with the IP-XACT specification.
coreAssembler – an open IP assembly tool that automatically generates the interconnect and configured RTL, as well as documenting the block and system configuration details and design testbench. When combined with coreBuilder, entire subsystems can be packaged as coreKits enabling the easy creation configurable market targeted platforms. In addition to assembly and configuration designers are able to generate a starting testbench configured for the design so they can begin to validate there design. coreAssembler also will generate the IP-XACT XML for the design.
coreConsultant – the utility package for configuring, implementing and validating individual IP blocks packaged with coreBuilder. coreConsultant will also generate the IP-XACT XML for the IP block.
The Synopsys family of coreTools is a comprehensive set of intellectual property (IP) packaging and integration tools for
use in a knowledge-based design and verification flow. The tools enable designers to realize maximum productivity gains
when using IP in their desing. By using an IP-based design and verification flow with IP packaged for assembly, the risk
configuration, and subsystem integration errors is virtually eliminated, and designers have seen over a 60% reduction in
SoC or platform design time and achieve the highest QoR in the implementation of the design
Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia.
Owner: Synopsys Inc.
Product Name: coreTools
Version: vW-2024.09-SP2
Supported Architectures: x86_64
Languages Supported: english
System Requirements: Linux *
Synopsys CoreTools vW-2024.09-SP2 | 644 mb
Download
*