Xilinx Vitis Core Development Kit 2025.1.1 /Vitis, Vivado, PetaLinux/ x64 (Linux, Windows) [2025, ENG]

Year/Release Date: 2025
Version: 2025.1.1
Developer: Xilinx Inc.
Bit depth: 64-bit
Interface language: English
Tablet: present, also activates the IP cores built into the package
Advertising: none
System requirements:
Linux, 64-bit:
- Red Hat Enterprise Workstation/Server: 8.10, 9.2, 9.3, 9.4, 9.5
- SUSE Linux Enterprise: 15 SP4
- Amazon Linux 2 AL2 LTS
- AlmaLinux: 8.10, 9.4, 9.5
- Ubuntu: 22.04.2 - 22.04.5 LTS, 24.04 LTS, 24.04.1 LTS (requires libtinfo.so.5 according to *)
- Rocky Linux: 8.10
Windows 10, 64-bit:
- Professional and Enterprise 22H2
Windows 11 64-bit:
- 23H2, 24H2
RAM: 32 GB (64 GB recommended)
Hard disk space for a full installation is ~200 GB; Vivado Lab Edition requires ~5 GB.
Description: The Vitis unified software platform enables embedded software and accelerated application development on heterogeneous Xilinx platforms, including FPGAs, SoCs, and Versal ACAP.
Additional information:
Starting with Vivado 2023.1, compilation to the VHDL-2019 standard is supported. Vivado 2025.1 added the ability to simulate VHDL-2019 code.
This version includes significant changes to support the Versal family. - Vivado Release Notes
Download
115GB

Year/Release Date: 2025
Version: 2025.1.1
Developer: Xilinx Inc.
Bit depth: 64-bit
Interface language: English
Tablet: present, also activates the IP cores built into the package
Advertising: none
System requirements:
Linux, 64-bit:
- Red Hat Enterprise Workstation/Server: 8.10, 9.2, 9.3, 9.4, 9.5
- SUSE Linux Enterprise: 15 SP4
- Amazon Linux 2 AL2 LTS
- AlmaLinux: 8.10, 9.4, 9.5
- Ubuntu: 22.04.2 - 22.04.5 LTS, 24.04 LTS, 24.04.1 LTS (requires libtinfo.so.5 according to *)
- Rocky Linux: 8.10
Windows 10, 64-bit:
- Professional and Enterprise 22H2
Windows 11 64-bit:
- 23H2, 24H2
RAM: 32 GB (64 GB recommended)
Hard disk space for a full installation is ~200 GB; Vivado Lab Edition requires ~5 GB.
Description: The Vitis unified software platform enables embedded software and accelerated application development on heterogeneous Xilinx platforms, including FPGAs, SoCs, and Versal ACAP.
Additional information:
Starting with Vivado 2023.1, compilation to the VHDL-2019 standard is supported. Vivado 2025.1 added the ability to simulate VHDL-2019 code.
This version includes significant changes to support the Versal family. - Vivado Release Notes
Download
115GB